The fabrication of semiconductor devices such as logic and memory devices typically includes processing a semiconductor device using a number of fabrication processes and characterization processes to form various features and multiple layers of the semiconductor device. Select fabrication processes utilize photomasks/reticles to print features on a semiconductor device such as a wafer. As semiconductor devices become smaller and smaller laterally and extended vertically, it becomes critical to develop enhanced characterization processes with increased sensitivity and throughput.
Excursions (e.g., a random and/or significant topography deviation by a fabrication process or fabrication tool from nominal specification) may cause the semiconductor devices to develop defects. Select characterization processes for locating excursions and/or defects include wafer geometry metrology processes (e.g., pattern wafer geometry (PWG) metrology, topography metrology, or the like) and wafer inspection processes (e.g., die-to-die inspection).
Wafer geometry metrology processes, however, may lose detailed information about the topography of the wafer surface, which may limit the issue-finding capability of full wafer topography. In addition, wafer inspection processes may not respond to z-height and/or surface geometry defects. As such, geometry-induced defects may not be solely covered by either wafer geometry metrology processes or wafer inspection processes.
Therefore, it would be advantageous to provide a system and method that cures the shortcomings described above.